Contador Up Down

Contador binario de n bits

  • n es el numero de bites y se cambia con generic map (n => #) antes del por map
  • Enable ='0'  =>mantiene su salida
  • Enable ='1'  =>
    • ld='1'               => caga entrada en la salida
    • U_notD = '1'  => incrementa en uno la salida
    • U_notD = '0' => decrementa en uno la salida

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;

ENTITY contador_U_D IS
generic (n: integer :=4);
PORT(clock,reset,enable,ld,U_notD : IN STD_LOGIC;
Ent: in STD_LOGIC_vector (n-1 downto 0);
Q : Buffer STD_LOGIC_VECTOR (n-1 downto 0));
END contador_U_D;

ARCHITECTURE sol OF contador_U_D IS
BEGIN
PROCESS(clock,reset)
BEGIN
if reset='0' then Q <= (others =>'0');
elsif (clock'event and clock='1') then
if enable = '1' then
if ld = '0' then
if U_notD = '1' then Q <= (Q+1);
else Q <= (Q-1);
end if;
else Q<= Ent;
end if;
end if;
end if;
END PROCESS;
END sol;