Componentes vhdl

Acumulador de n bits

• borrar = '1'     => acumulador se pone ne cero
• si suma = '1'   => se coloca en la salida la suma de la salida mas la entrada

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;

ENTITY acumulador IS
generic (n: integer:=5);
PORT(reset, suma : IN STD_LOGIC;
A : IN STD_LOGIC_VECTOR(n-1 downto 0);
clock : IN STD_LOGIC;
borrar: IN STD_LOGIC;
Q : BUFFER STD_LOGIC_VECTOR (n-1 downto 0));
END acumulador;

ARCHITECTURE sol OF acumulador IS
BEGIN
PROCESS(clock, reset,borrar)
BEGIN
if (reset='0' or borrar='1') then Q<=(others => '0');
elsif (clock='1' and clock'event) then
if(suma='1') then Q<=Q+A; end if;
end if;
END PROCESS;
END sol;